Low leakage current SRAM array

ABSTRACT

An SRAM array is disclosed. The SRAM array includes a plurality of SRAM cells. In one embodiment, the SRAM cells are 6-T SRAM cells that further includes a voltage bias device. The voltage bias device raises the voltage level of a low voltage rail V ss  such that the plurality of SRAM cells are connected to a raised low voltage rail.

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates to integrated circuits, and more particularly, to a SRAM array having reduced bitline leakage current.

BACKGROUND OF THE INVENTION

[0002] Metal oxide semiconductor (MOS) static random access memory (SRAM) arrays are comprised of an array of SRAM cells. The SRAM cells are read, erased, and written to by means of bitlines (BL) and wordlines (WL). In one common design, the SRAM cells consist of load elements in a flip-flop configuration, together with two select transistors.

[0003]FIG. 1 is a schematic circuit diagram of a six-transistor (6T) SRAM cell 101 that is commonly and widely used in SRAM memory arrays. The SRAM cell 101 is known in the art as a 6T SRAM cell. The SRAM cell 101 includes N-type MOS (NMOS) transistors N1 and N2 (hereinafter transistors N1 and N2) coupled between V_(ss) (typically ground) and nodes A and B, respectively. Nodes A and B are further coupled to V_(DD) by pull-up P-type MOS (PMOS) transistors P1 and P2 (hereinafter transistors P1 and P2), respectively. Node A is further coupled to the gates of transistors P2 and N2 and node B is similarly coupled to the gates of transistors P1 and N1.

[0004] Information is stored in SRAM cell 101 in the form of voltage levels in the flip-flop formed by the two cross-coupled inverters formed by transistors P1, N1 and P2, N2, respectively. In particular, when node A is at a logic low state (the voltage of node A being approximately equal to V_(ss)), transistor P2 is on (in a low resistance state or conducting) and transistor N2 is off (in a high resistance state or non conducting). When transistor P2 is on and transistor N2 is off, node B is at a logic high state (the voltage of node B is pulled up to approximately V_(DD)). Further, when node B is at a logic high state, transistor P1 is off and transistor N1 is on. When transistor P1 is off and transistor N1 is on, node A is at a logic low state (the voltage of node A is pulled down to approximately V_(ss)). In this manner, SRAM cell 101 remains in a latched state.

[0005] Nodes A and B are further coupled to a “bitline” and a “bitline-not” by NMOS select transistors N3 and N4 (hereinafter transistors N3 and N4), respectively. The gates of transistors N3 and N4 are coupled to a word line to enable read and write operations, as those skilled in the art will understand.

[0006] A read operation is performed by turning on the word line and allowing one side of the SRAM cell to start pulling down on one line of the bitline pair. For example, if node A is low and the word line is pulled high, then a current will flow through select transistor N3 and transistor N1 to ground or V_(ss).

[0007] When node A is low and the word line is low, the SRAM cell 101 has a leakage current 103 that flows from the bitline through the select transistor N3 and transistor N1 down to ground or V_(ss).

[0008] As the size of the SRAM cells decreases, the amount of read current produced by the SRAM cell also decreases, particularly as the supply voltage V_(cc) is lowered as technology advances. As the amount of read current decreases, the leakage current becomes larger relative to the read current, thereby making it more difficult to accurately read the SRAM cell. Thus, it is desirable to lower the amount of leakage current from each SRAM cell.

[0009] One method of solving this problem is to reduce the number of SRAM cells per bitline, thereby reducing the overall amount of leakage current. However, this increases the amount of overhead devices such as sense amplifiers, column multiplexer circuitry, etc. for a given number of SRAM cells.

[0010] Another approach is to increase the channel length of the transistors in the SRAM cell. However, this increases the SRAM cell size. Furthermore, effect of this approach is limited, as the transistor devices get smaller.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention is illustrated by way of example and not limitation in the accompanying Figures.

[0012]FIG. 1 is a schematic diagram of a prior art SRAM cell.

[0013]FIG. 2 is a schematic diagram of an SRAM cell incorporating the present invention.

[0014]FIG. 3 is a schematic diagram of an SRAM array incorporating an alternative embodiment of the present invention.

DETAILED DESCRIPTION

[0015] Methods and apparatus' for a SRAM memory array having reduced leakage current are disclosed. The subject of the invention will be described with reference to numerous details set forth below, and the accompanying drawings will illustrate the invention. The following description of the drawings are illustrative of the invention and are not to be construed as limiting the invention. Numerous specific details are described to derive a thorough understanding of present invention. However, in certain circumstances, well known, or conventional details are not described in order not to obscure the present invention in detail.

[0016] In general, the amount of leakage current through a channel of a transistor follows an exponential relationship with the gate to source voltage difference (V_(gs)), in the sub threshold region of transistor behavior. Empirically, it has been determined to increase about 10 times per 100 millivolt increase in V_(gs) in the sub threshold region. Moreover, it has an approximately linear relationship with V_(cc), the supply voltage.

[0017] The magnitude of the read current of an SRAM cell 101, shown in FIG. 1, is essentially the saturation current of the pull-down transistors N3 and N4. This is proportional to the square of the difference between V_(cc) and V_(t), the threshold voltage of the pull-down transistors. Therefore, with respect to V_(cc), the read current declines faster than the leakage current as the supply voltage (V_(cc) ) is lowered.

[0018] With these principles in mind, FIG. 2 shows an SRAM cell 201 formed in accordance with the present invention. In many respects, the SRAM cell 201 is substantially similar to the SRAM cell 101 of FIG. 1. However, as seen in FIG. 2, the sources of the pull-down transistors N1 and N2 are not connected directly to V_(ss) (ground). Instead, the sources of the pull-down transistors N1 and N2 are connected to V_(ss) (ground) through a bias device 203. The bias device 203 can be a transistor that produces a small positive voltage on its' source node, equivalent to the voltage drop across the channel of the bias transistor 203. Typically, this voltage drop is on the order of 0.1 volts. Consequently, the pulldown transistors N1 and N2 transfer the positive biasing voltage to the source nodes of the access transistors N3 and N4.

[0019] By raising the voltage on the sources of the NMOS transistors N1 and N2 in the SRAM 201 slightly above V_(cc), the voltage between gate to source (V_(gs)) of transistors N1 and N2 is now negative. The threshold voltage V_(t) is raised as the reverse-biased source junction depletes part of the channel. These effects combine to reduce leakage current exponentially, while reducing the read current only slightly.

[0020] Further, although a biasing transistor 203 is used to raise the level of the source nodes of the transistors N1 and N2, any device that can raise the voltage on the source nodes of transistors N1 and N2 above VSS may be used. As one example, a controllable voltage source, or a simple resistor, may be used. In one embodiment, the amount of bias voltage used to raise V_(ss) is on the order of 0.1 volts. However, higher or lower bias voltages may be implemented to accommodate design variations. For example, by reducing the size of transistors 203, a higher bias voltage may be applied to the sources of the transistors N1 and N2. This approach further decreases the leakage current, however at the expense of a lower read current signal. As another example, by a “larger” bias transistor having a low voltage drop across its' channel may be used to apply a lower bias voltage to the sources of the transistors N1 and N2. This approach results in a lower decrease in the leakage current, however with the benefit of a higher read current signal. Thus, the present invention may be modified to fit the requirements of a particular integrated circuit.

[0021] Moreover, although only a single SRAM cell 201 is shown in FIG. 2, the biasing transistor 203 is connected to all of the pull-down transistors N1 and N2 of all of the SRAM cells 201 in a single column in the SRAM memory array. Thus, only a single bias transistor 203 is required for each column of the memory array. Further, in one embodiment, the bias transistor 203 is always in the “on” state by biasing the gate of the bias transistor 203 to the supply voltage V_(cc).

[0022] As noted above, the use of the bias transistor 203, while decreasing the leakage current, also has the undesirable effect of lowering the read current. Thus, turning to FIG. 3, in an alternative embodiment, a two level bias transistor scheme may be used. In particular, the bias transistor may comprise a small bias transistor 301 and a large bias transistor 303.

[0023]FIG. 3 shows two portions of an SRAM array. The first portion 305 is being accessed, while the second portion 307 is not being accessed. In the second portion 307 of the SRAM array that is not being accessed (read), only the small bias transistor 301 is turned “on” to maintain a relatively high raised V_(ss) level. This has the effect of significantly reducing leakage current.

[0024] In the first portion 305 of the SRAM array that is being accessed (read), both the small bias transistor 301 and the large bias transistor 303 are turned on. By turning on the large bias transistor 303, this will tend to bring the source node of the transistors of the SRAM cells 201 closer to ground (V_(ss)). This has the effect of reducing leakage current while maintaining a good read current.

[0025] Thus, the selective scheme of FIG. 3 is beneficial at low V_(cc) supply voltage conditions where the read current is small. The precise block size should be determined by trade offs between acceptable read current/leakage current ratios and cost and increased area required by the two biasing transistors for each portion of the SRAM array. For blocks of the memory array that are “on,” both the small biasing transistor 301 and the large biasing transistor 303 are turned “on.” This results in the virtual “V_(ss)” node near ground and allows the memory array to sink read current.

[0026] By lowering the leakage current, the present invention allows a higher number of SRAM cells per bitline, thereby reducing the amount of overhead for an array of given size. Further, the present invention requires relatively little overhead, using only a few transistor devices for a large number of SRAM cells and little additional routing overhead. Finally, the present invention can maintain channel leakage current small relative to read current even at low supply voltages.

[0027] While specific embodiments of applications of the present invention have been illustrated and described, it is to be understood that the invention is not limited to the precise configuration and components disclosed herein. Various modifications, changes, and variations, which will be apparent to those skilled in the art, may be made in the arrangement, operation, in details of the methods and systems of the present invention disclosed herein without departing from the spirit and scope of the invention.

[0028] These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be used to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established canons of claim interpretation. 

What is claimed is:
 1. An SRAM array comprising: a plurality of SRAM cells, each of said SRAM cells adapted for connection to a wordline, a power supply V_(dd), a bitline, a bitline-not, and a low voltage rail V_(ss); and a bias device to raise the voltage level of said low voltage rail V_(ss) to a raised low voltage rail such that said plurality of SRAM cells are connected to said raised low voltage rail.
 2. The array of claim 1 wherein said bias device is a bias transistor between said low voltage rail V_(ss) and said raised low voltage rail.
 3. The array of claim 1 wherein said bias device is a resistor.
 4. The array of claim 1 wherein said bias device is a voltage source between said low voltage rail V_(ss) and said raised low voltage rail.
 5. The array of claim 1 wherein SRAM cells in a column are connected to a single bias device.
 6. The array of claim 5 wherein each column of SRAM cells has a single bias device.
 7. The array of claim 1 wherein said plurality of SRAM cells are 6T SRAM cells.
 8. The array of claim 1 wherein said raised low voltage rail is about 0.1 volts higher than said low voltage rail V_(ss).
 9. The array of claim 1 wherein said SRAM array is partitioned into at least a first portion of SRAM cells and a second portion of SRAM cells, said first portion of SRAM cells having a first biasing means and said second portion of SRAM cells having a second biasing means.
 10. The array of claim 8 wherein said first biasing means and said second biasing means include a large bias transistor and a small bias transistor.
 11. The array of claim 9 wherein said small bias transistors for said first biasing means and second biasing means are on.
 12. The array of claim 10 wherein said large bias transistor of said first biasing means is on only if the SRAM cells of said first portion of SRAM cells are being read.
 13. The array of claim 11 wherein said large bias transistor of said first biasing means is off if the SRAM cells of said first portion of SRAM cells are not being read.
 14. A SRAM memory cell comprising: a first select transistor connected between a bitline and a first node, a gate of said first select transistor connected to a wordline; a second select transistor connected between a bitline-not and a second node, a gate of said second select transistor connected to said wordline; a first load transistor connected between said first node and a power supply rail; a second load transistor connected between said second node and said power supply rail; a voltage bias device connected to a low voltage rail V_(ss); an N1 transistor coupled between said first node and said voltage bias device; and an N2 transistor coupled between said second node and said voltage bias device.
 15. The cell of claim 14 wherein said voltage bias device is a transistor between said low voltage rail V_(ss) and said N1 transistor and N2 transistor.
 16. The cell of claim 14 wherein said voltage bias device is a voltage source between said low voltage rail V_(ss) and said N1 transistor and N2 transistor.
 17. The cell of claim 14 wherein said voltage bias device raises said low voltage rail V_(ss) by about 0.1 volts.
 18. The cell of claim 14 wherein said voltage bias device is a resistor between said low voltage rail V_(ss) and said N1 transistor and N2 transistor.
 19. A SRAM cell comprising: a 6-T SRAM cell for connection to a power supply rail V_(dd) and a raised low voltage rail; and a voltage bias device to raise the voltage level of a low voltage rail V_(ss) such that said 6-T SRAM cell is connected to said raised low voltage rail.
 20. The cell of claim 19 wherein said voltage bias device is a bias transistor between said low voltage rail V_(ss) and said raised low voltage rail.
 21. The cell of claim 19 wherein said voltage bias device is a voltage source between said low voltage rail V_(ss) and said raised low voltage rail.
 22. The cell of claim 19 wherein said voltage bias device raises said low voltage rail V_(ss) by about 0.1 volts.
 23. The cell of claim 19 wherein said voltage bias device is a resistor between said low voltage rail V_(ss) and said N1 transistor and N2 transistor.
 24. A method of reducing bitline leakage current in a SRAM cell comprising: raising the voltage of a low voltage rail V_(ss) by a voltage amount using a voltage bias device; and connecting said SRAM cell to a bitline, a wordline and said low voltage rail.
 25. The method of claim 24 wherein said voltage amount is about 0.1 volts.
 26. The method of claim 24 wherein comprising: raising the voltage of said low voltage rail V_(ss) only if said SRAM cell is not being read.
 27. The method of claim 24 wherein comprising: disengaging said voltage bias device if said SRAM cell is being read. 